NVIDIA Details How NVLink Fusion Connects Custom XPUs
NVIDIA published a technical breakdown of NVLink Fusion on August 24, 2026, explaining how a company's own custom accelerators connect to NVIDIA rack infrastructure. Everything below comes from that first party post. Note that NVLink Fusion is an existing NVIDIA program, so this is NVIDIA making its case for it, not a launch announcement.
Transcript
Today NVIDIA laid out how NVLink Fusion connects custom XPUs to its own AI factory infrastructure.
Hyperscalers building custom XPUs must also design networking and rack scale architecture. NVIDIA says that path is complex and costly. NVLink Fusion connects those chips to its infrastructure instead.
Sixth generation NVLink spans a seventy two XPU domain. End to end latency is three times lower than off the shelf Ethernet. Packet rate is ten times higher.
Adopters reuse the MGX rack architecture and the Vera Rubin supply chain. Operators can begin buildout before fixing the final silicon mix. Reference compute trays are fully liquid cooled.
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Sources
Every claim in this video comes from the top ranking coverage of this topic. The claims and where each one came from:
- Deploying custom silicon with leading AI infrastructure enables hyperscalers and AI-native companies to build flexible AI factories that combine specialization with scale.(NVIDIA's official announcement, How XPUs Meet a World-Class AI Factory, published August 24, 2026)
- To generate intelligence at scale, AI factories run continuously, and their economics are defined by delivered output: tokens per second, tokens per watt, cost per token, utilization and uptime.(NVIDIA's official announcement, How XPUs Meet a World-Class AI Factory, published August 24, 2026)
- Hyperscalers and AI-native companies building custom XPUs must consider not just XPU design, but the design and development of the entire AI platform, including scale-up and scale-out networking, rack-scale architecture, production factory software and a robust supplier ecosystem.(NVIDIA's official announcement, How XPUs Meet a World-Class AI Factory, published August 24, 2026)
- At AI factory scale, this path is complex and costly, and represents a fundamental obstacle to getting XPUs to market quickly.(NVIDIA's official announcement, How XPUs Meet a World-Class AI Factory, published August 24, 2026)
- NVLink Fusion delivers on that need, connecting XPUs to NVIDIA's world-leading AI infrastructure to increase performance, accelerate time to market and mitigate risk for semi-custom AI factories.(NVIDIA's official announcement, How XPUs Meet a World-Class AI Factory, published August 24, 2026)
- NVLink Fusion brings XPUs into the NVIDIA NVLink scale-up domain. Sixth-generation NVLink provides leading high-bandwidth, low-latency networking across a 72-XPU domain.(NVIDIA's official announcement, How XPUs Meet a World-Class AI Factory, published August 24, 2026)
- The end-to-end latency for XPU-to-XPU transfers is 3x lower than alternative solutions based on off-the-shelf Ethernet, and the packet rate is 10x higher.(NVIDIA's official announcement, How XPUs Meet a World-Class AI Factory, published August 24, 2026)
- future NVLink roadmap configurations include domains of up to 1,152 accelerators and co-packaged optics.(NVIDIA's official announcement, How XPUs Meet a World-Class AI Factory, published August 24, 2026)
- NVLink Fusion adopters can also use the NVIDIA MGX rack-scale architecture and the same supply chain used for MGX-based systems such as NVIDIA Vera Rubin NVL72(NVIDIA's official announcement, How XPUs Meet a World-Class AI Factory, published August 24, 2026)
- Reference compute trays feature 100% liquid cooling with no fans, cables or hoses, and allow trays to be removed while the rest of the rack remains operational.(NVIDIA's official announcement, How XPUs Meet a World-Class AI Factory, published August 24, 2026)
- Operators can move forward with buildout while deferring the precise silicon mix, then reprovision capacity as workload demand, silicon supply and business priorities change.(NVIDIA's official announcement, How XPUs Meet a World-Class AI Factory, published August 24, 2026)